Tuesday, June 11, 2002, 4:30 PM - 6:00 PM | Room: 288 SESSION 14    Fabric-Driven Logic Synthesis    Chair: Tiziano Villa - Parades, Roma, ITA    Organizers: Malgorzata Marek-Sadowska, Steven Nowick    Papers in this section discuss synthesis approaches which target specific fabrics. The first paper proposes a new regular layout structure and discusses logic synthesis for it. The second paper describes a modified Bellman-Ford algorithm for cycle stealing in FPGAs. The third paper shows how layout information can improve carry-save adder designs.      14.1 River PLAs: A Regular Circuit Structure    Speaker(s): Fan Mo - Univ. of California, Berkeley, CA    Author(s): Fan Mo - Univ. of California, Berkeley, CA Robert K. Brayton - Univ. of California, Berkeley, CA      14.2 Cycle Stealing Boosts FPGA Performance    Speaker(s): John P. Fishburn - Agere Systems, Inc., Murray Hill, NJ    Author(s): William B. Andrews - Lattice Semiconductor, Inc., Allentown, PA Barry K. Britton - Lattice Semiconductor, Inc., Allentown, PA Xiaotao Chen - Lattice Semiconductor, Inc., Allentown, PA Alfred E. Dunlop - Consultant, Murray Hill, NJ John P. Fishburn - Agere Systems, Inc., Murray Hill, NJ Harold N. Scholz - Lattice Semiconductor, Inc., Allentown, PA      14.3 Layout-Aware Synthesis of Arithmetic Circuits    Speaker(s): Junhyung Um - KAIST, Taejon, Korea    Author(s): Junhyung Um - KAIST, Taejon, Korea Taewhan Kim - KAIST, Taejon, Korea